In the development of a semiconductor integrated circuit, it is important to accurately identify causes of a circuit bug at the time of design and of a circuit malfunction due to the operating frequency at an early stage. In the recent development of semiconductor integrated circuits, it has become difficult to accurately grasp bugs and circuit malfunctions particularly due to the problems described below.
In other words, as the scale of circuits increases due to the improved performance, it is difficult to achieve accurate simulation at the time of design, the number of bugs increases, and understanding a failure is difficult due to complex malfunctions of a plurality of circuits. Further, since the operating frequency increases in order to achieve high-speed operation, the frequencies cannot be exhaustively simulated, resulting in increased bugs. Further, it is difficult to understand causes of malfunctions due to an increase in malfunctions caused by high-speed operation and to an increase in the level of analysis. Further, since circuits are optimized in order to reduce chip areas, the number of malfunctions increases due to the operation changes before and after the optimization, and complex malfunctions of a plurality of optimized blocks also increase. Furthermore, since operating power supply voltages are lowered in order to reduce power consumption, susceptibility to process, temperature, and noise increases, resulting in increased malfunctions. Further, due to the miniaturization of processes, malfunctions caused by processes (e.g., leak paths and defective cells) increase, and the increase in the level of analysis becomes an issue.
In order to solve these problems and improve the accuracy and speed of analysis/testing, various semiconductor integrated circuits comprise BIST circuits and scan circuits, provided only for performing tests. However, depending upon the scale of the circuit, a decrease in the operating speed and an increase in malfunctions may occur due to the fact that chip areas get larger and internal paths become more complex.
Patent Document 1 describes a semiconductor memory device having a redundant cell array provided in a memory cell array, and a test time is reduced by providing a data terminal specifically for the redundant cell array and performing a test on cells other than the redundant cells in parallel.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-269993A, which corresponds to US Patent Publication 2002/131307.